Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

Author： Gan Kwang-Jow  

Publisher： Springer Publishing Company

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.59, Iss.2, 2009-05, pp. : 161-167

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

By Eggersglüß Stephan  

Journal of Electronic Testing, Vol. 26, Iss. 3, 2010-06 ,pp. : 307-322

Springer Publishing Company

Access to resources Recommend Favorite

BiCMOS domino: a novel high-speed dynamic BiCMOS logic

By Menon Sankaran M.   Jayasumana Anura P.   Malaiya Yashwant K.  

International Journal of Electronics, Vol. 83, Iss. 2, 1997-08 ,pp. : 177-190

Taylor & Francis Ltd

Access to resources Recommend Favorite

A SiGe BiCMOS 24-GHz receiver front-end for automotive short-range radar

By Ragonese Egidio  

Analog Integrated Circuits and Signal Processing, Vol. 67, Iss. 2, 2011-05 ,pp. : 121-130

Springer Publishing Company

Access to resources Recommend Favorite

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

By Herzel Frank  

Analog Integrated Circuits and Signal Processing, Vol. 65, Iss. 1, 2010-10 ,pp. : 21-32

Springer Publishing Company

Access to resources Recommend Favorite

Modelling and testing for bridging faults in CMOS and BiCMOS combinational circuits

By Ismaeel Asad A.   Bhatnagar Rakesh  

International Journal of Electronics, Vol. 83, Iss. 4, 1997-10 ,pp. : 529-540

Taylor & Francis Ltd

Access to resources Recommend Favorite