Fast tabular technique for fixed-polarity Reed-Muller logic with inherent parallel processes

By Tan E. C.   Yang H.  

International Journal of Electronics, Vol. 85, Iss. 4, 1998-10 ,pp. : 511-520

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Mapping of fixed polarity Reed-Muller coefficients from minterms and the minimization of fixed polarity Reed-Muller expressions

By Khan Md. Mozammel Huq Azad   Alam Md. Shamsul  

International Journal of Electronics, Vol. 83, Iss. 2, 1997-08 ,pp. : 235-248

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Mapping of on-set fixed polarity Reed-Muller coefficients from on-set canonical sum of products coefficients and the minimization of pseudo Reed-Muller expressions

By Khan Md. Mozammel Huq Azad   Alam Md. Shamsul  

International Journal of Electronics, Vol. 86, Iss. 3, 1999-03 ,pp. : 255-268

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Optimization of multi-output fixed-polarity Reed-Muller circuits using the genetic algorithm

By Yang H.   Tan E. C.  

International Journal of Electronics, Vol. 86, Iss. 6, 1999-06 ,pp. : 663-670

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A new approach to generate fixed-polarity Reed-Muller expansions for completely and incompletely specified functions

By Habib Maki K.  

International Journal of Electronics, Vol. 89, Iss. 11, 2002-11 ,pp. : 845-876

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