Author： Jang Sheng-Lyang Yang Chang-Hao Liu Cheng-Chen Juang Miin-Horng
Publisher： Taylor & Francis Ltd
ISSN： 1362-3060
Source： International Journal of Electronics, Vol.96, Iss.7, 2009-07, pp. : 691-697
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Abstract
A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 m CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of -5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38-2.31 GHz.
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