Network Processor Design :Issues and Practices ( Volume 3 )

Publication subTitle :Issues and Practices

Publication series :Volume 3

Author: Franklin   Mark A.;Crowley   Patrick;Hadimioglu   Haldun  

Publisher: Elsevier Science‎

Publication year: 2005

E-ISBN: 9780080512501

P-ISBN(Paperback): 9780120884766

P-ISBN(Hardback):  9780120884766

Subject: TN4 microelectronics, integrated circuit (IC)

Language: ENG

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Description

The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors.

Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.

Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.

  • Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule
  • Presents current research in network processor design in three distinct areas:
    • Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University.
    • Tools and Techniqu

Chapter

Front Cover

pp.:  1 – 4

Copyright Page

pp.:  5 – 8

About the Editors

pp.:  6 – 16

Contents

pp.:  8 – 6

Preface

pp.:  16 – 18

Chapter 1. Network Processors: New Horizons

pp.:  18 – 26

Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches

pp.:  26 – 50

Chapter 3. Efficient Packet Classification with Digest Caches

pp.:  50 – 72

Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express

pp.:  72 – 98

Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet

pp.:  98 – 116

Chapter 6. A Hardware Platform for Network Intrusion Detection and Prevention

pp.:  116 – 136

Chapter 7. Packet Processing on a SIMD Stream Processor

pp.:  136 – 162

Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations

pp.:  162 – 190

Chapter 9. RNOS—A Middleware Platform for Low-Cost Packet-Processing Devices

pp.:  190 – 214

Chapter 10. On the Feasibility of Using Network Processors for DNA Queries

pp.:  214 – 236

Chapter 11. Pipeline Task Scheduling on Network Processors

pp.:  236 – 262

Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs

pp.:  262 – 296

Chapter 13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures

pp.:  296 – 326

Index

pp.:  326 – 336

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