Author： Venkatachalam Vasanth Franz Michael Probst Christian W.
Publisher： Inderscience Publishers
ISSN： 1741-1068
Source： International Journal of Embedded Systems, Vol.3, Iss.1-2, 2007-12, pp. : 17-30
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Abstract
Many dynamic voltage scaling algorithms rely on measuring hardware events (such as cache misses) for predicting how much a workload can be slowed down with acceptable performance loss. The events measured, however, are at best indirectly related to execution time and clock frequency. By relating these two indicators logically, we propose a new way of predicting a workload's compute-boundedness that is based on direct observation, and only requires measuring the total execution cycles for the two highest clock frequencies. Our predictor can be used to develop dynamic voltage scaling algorithms that are more system-aware than current approaches.
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