An efficient single unit T‐box/T−1‐box implementation for 128‐bit AES on FPGA

E-ISSN： 1939-0122|8|9|1725-1731

ISSN： 1939-0114

Source： SECURITY AND COMMUNICATION NETWORKS (ELECTRONIC), Vol.8, Iss.9, 2015-06, pp. : 1725-1731

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