A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation

Author： Ghamkhari Seyedeh   Ghaznavi-Ghoushchi Mohammad  

Publisher： Springer Publishing Company

ISSN： 0278-081X

Source： Circuits, Systems, and Signal Processing, Vol.33, Iss.4, 2014-04, pp. : 1245-1259

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Related content

A Low-Power 100 MHz Analog FIR Filter for PRML Equalization

By Choi J.  

Analog Integrated Circuits and Signal Processing, Vol. 28, Iss. 3, 2001-09 ,pp. : 225-238

Springer Publishing Company

Access to resources Recommend Favorite

A low power 8-tap digital FIR filter for PRML read channels

By Ki Hoon-Jae   Lee Cheon-Su   Paik Woo-Hyun   Hwang In-Chul   Chae Kwan-Yeob   Yoo Jang-Sik   Kim Soo-Won  

International Journal of Electronics, Vol. 87, Iss. 4, 2000-04 ,pp. : 445-455

Taylor & Francis Ltd

Access to resources Recommend Favorite

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

By Wang R.  

Analog Integrated Circuits and Signal Processing, Vol. 28, Iss. 2, 2001-08 ,pp. : 149-160

Springer Publishing Company

Access to resources Recommend Favorite

Design of low-power silicon articulated microrobots

By Yeh Richard   Hollar Seth   Pister Kristofer S. J.  

Journal of Micromechatronics, Vol. 1, Iss. 3, 2001-07 ,pp. : 191-203

VSP

Access to resources Recommend Favorite

A Low-Power Reconfigurable Analog Filter for UMTS/WLAN Receivers

By D'amico Stefano   Giannini Vito   Baschirotto Andrea  

Analog Integrated Circuits and Signal Processing, Vol. 46, Iss. 1, 2006-01 ,pp. : 65-72

Springer Publishing Company

Access to resources Recommend Favorite