Chapter
2.1.4 The small-signal equivalent circuit of the two-terminal MOS (for p-type substrates)
2.1.5 The three-terminal MOS structure and the unified charge-control model (UCCM)
2.1.6 The pinch-off voltage
2.1.7 The Pao–Sah exact I-V model
2.1.8 A charge-sheet formula for the current
2.1.9 A charge-control compact model
2.2 A design-oriented MOSFET model
2.2.1 Forward and reverse components of the drain current
2.2.2 Universal dc characteristics
2.2.3 MOSFET operation in weak and strong inversion
2.2.4 Small-signal transconductances
2.3 Dynamic MOSFET models
2.3.2 Capacitive coefficients
2.3.3 Capacitances of the extrinsic transistor
2.3.4 A non-quasi-static small-signal model
2.3.5 A quasi-static small-signal model
2.3.6 The intrinsic transition frequency
2.4 Shorthannel effects in MOSFETs
2.4.2 Velocity saturation
2.4.3 Channel-length modulation
2.4.4 Drain-induced barrier lowering
2.4.5 Output conductance in saturation
2.4.6 Gate tunneling currents
A2.1 Semiconductor charges
A2.2 Drain- and source-associated inversion charges
A2.3 Summary of n-channel MOSFET equations: UCCM, current, charges, transconductances, and capacitances including short-channel effects
A2.4 An alternative low-frequency small-signal model of the MOSFET in saturation
3 CMOS technology, components, and layout techniques
3.1 An overview of CMOS technology
3.1.1 Basic process steps in monolithic IC fabrication
3.1.2 Generic deep-submicron CMOS process flow
3.1.2.1 Transistor fabrication
3.1.2.2 MOSFET structure in deep-submicron processes
3.1.3 Main parameters in 350- 180- and 90-mm processes
3.2 Devices in CMOS technology
3.2.1.1 Polysilicon resistors
3.2.1.2 Implanted and diffused resistors
3.2.1.3 The MOS transistor as a resistor
3.2.2.1 Metal–insulator–metal (MIM) capacitors
3.2.2.2 Metal–oxide–semiconductor (MOS) capacitors
3.2.2.3 MOSFET gate capacitors
3.2.4 Bipolar transistors
3.4.1 Optical lithography
3.4.1.1 Design for manufacturability
3.4.2 Mask layout and design rules
3.4.3.1 Layout for matching
3.4.3.3 Interdigitated layout
3.4.3.4 Series association of transistors
4 Temporal and spatial fluctuations in MOSFETs
4.2. Modeling the drainurrent fluctuations in MOSFETs
4.3 Thermal noise in MOSFETs
4.3.1 Channel thermal noise
4.3.2 Shorth-channel effects on channel thermal noise
4.4 Flicker noise in MOSFETs
4.5. Design-oriented noise models
4.5.1 Consistency of noise models
4.5.2 The thermal noise excess factor
4.5.3 Flicker noise in terms of inversion levels
4.5.4 The corner frequency
4.5.5 Two-port noise models
4.5.5.1 The correlation admittance
4.5.5.2 MOS-transistor equivalent input noise generators
4.6 Systematic and random mismatch
4.6.1 Pelgrom’s model of mismatch
4.6.2 (Mis)matching energy
4.6.3 The number-fluctuation mismatch model
4.6.4 The dependence of mismatch on bias, dimensions, and technology
4.6.5 Matching analysis of analog circuits
4.6.5.1 Monte Carlo simulation
4.6.5.2 Small-signal analysis of the mismatch sensitivity of a circuit
5.1 A simple MOS current mirror
5.1.1 The ideal current mirror
5.1.2 The two-transistor current mirror
5.1.3 Error caused by difference between drain voltages
5.1.4 Error caused by transistor mismatch
5.1.5 Small-signal characterization and frequency response
5.2 Cascode current mirrors
5.2.1 Self-biased cascode current mirrors
5.2.2 High-swing cascode current mirrors
5.3 Advanced current mirrors
5.4 Class-AB current mirrors
A.5.1 Harmonic distortion
6 Current sources and voltage references
6.1 A simple MOS current source
6.2 The Widlar current source
6.3 Self-biased current sources (SBCSs)
6.4 A MOSFET-only self-biased current source
6.5 Bandgap voltage references
6.5.1 The operating principle of the bandgap reference
6.5.2 CMOS bandgap references
6.5.3 A CMOS bandgap reference with sub-1-V operation
6.5.4 A resistorless CMOS bandgap reference
6.6 CMOS voltage references based on weighted VGS
6.7 A current-calibrated CMOS PTAT voltage reference
7.1 Common-source amplifiers
7.1.2 Diode-connected load
7.1.3 The intrinsic gain stage
7.1.4 Current source load
7.1.5 The push–pull amplifier (static CMOS inverter)
7.2 Common-gate amplifiers
7.4.1 Telescopic-and folded-cascode amplifiers
7.4.2 The gain-boost technique
7.5 Differential amplifiers
7.5.1 The source-coupled pair
7.5.1.1 The dc transfer characteristics
7.5.1.2 The common-mode input range
7.5.1.3 The input offset voltage
7.5.1.4 Small-signal analysis
7.5.2 Resistive-load differential amplifiers
7.5.3 Current-mirror-load differential amplifiers
7.5.3.1 Voltage transfer characteristics
7.5.3.2 The common-mode input range
7.5.3.3 The output voltage range
7.5.3.4 The offset voltage
7.5.3.5 Small-signal analysis – differential voltage gain
7.5.3.6 Small-signal analysis – common-mode gain and CMRR
7.5.3.7 Small-signal analysis – power-supply rejection ratio
7.5.3.9 The slew rate and settling response
7.6 Sizing and biasing of MOS transistors for amplifier design
7.6.1 Sizing and biasing of a common-source amplifier
7.6.2 The design procedure for a common-source amplifier
7.6.3 MOSVIEW: a graphical interface for MOS transistor design
7.7 Reuse of MOS analog design
7.7.1 Effects of scaling on analog circuits
7.7.2 Analog resizing rules
7.7.2.1 Constant-inversion-level scaling
7.7.2.2 Channel-length scaling: L→L/KL
7.7.2.3 A design-reuse example
8.1 Applications and performance parameters
8.1.1 The ideal operational amplifier
8.1.2 Basic applications of operational amplifiers
8.1.3 Performance parameters
8.2 The differential amplifier as an operational amplifier
8.2.1 The simple-stage differential amplifier
8.2.2 The telescopic-cascode differential amplifier
8.3 The symmetric operational amplifier
8.3.2 Small-signal characteristics and noise
8.4 The folded-cascode operational amplifiers
8.4.2 Small-signal characteristics and noise
8.5 Two-stage operational amplifiers
8.5.1 Cascade versus cascode amplifiers
8.5.2 DC characteristics of the two-stage amplifier
8.5.3 Small-signal characteristics of the two-stage Miller-compensated op amp
8.5.5 Alternative forms of compensation of the two-stage op amp
8.5.5.1 Elimination of the feedforward effect of CC using a buffer
8.5.5.2 Elimination of the feedforward effect of CC using a common-gate amplifier
8.5.5.3 A nulling resistor
8.6 Three-stage operational amplifiers
8.7 Rail-to-rail input stages
8.8 Class-AB output stages for operational amplifiers
8.9 Fully-differential operational amplifiers
A8.1 Systematic offset of a two-stage op amp
9 Fundamentals of integrated continuous-time filters
9.1 Basics of MOSFET-C filters
9.1.1 The MOSFET as a tunable resistor
9.1.2 Balanced transconductors for MOSFET-C filters
9.1.3 MOSFET-C integrators
9.2 Basics of OTA-C filters
9.2.3 Signal-to-noise ratio, dynamic range, and power
9.3 Digitally-programmable continuous-time filters
9.4 On-chip tuning schemes
A9.1 Distortion of the MOSFET operating as a resistor
10 Fundamentals of sampled-data circuits
10.1 MOS sample-and-hold circuits
10.1.1 Sample-and-hold basics
10.1.3 Switch on-resistance
10.1.4 Sampling distortion due to switch on-resistance
10.1.5 Linearization of the MOS sampling switch
10.1.6 Charge injection by the switch
10.1.6.1 Reducing injection errors
10.1.6.2 Rejecting injection errors
10.1.7 Low-voltage sample-and-hold circuits
10.1.9 Tradeoff between resolution and sampling rate in analog-to-digital converters
10.2 Basics of switched-capacitor filters
10.2.1 Basic principles of operation of switched-capacitor circuits
10.2.2 Switched-capacitor integrators
10.2.3 Offset compensation
10.2.5 Amplifier specifications
10.2.6 Low-distortion switched-capacitor filters
10.3 Switched-capacitor circuits as charge processors
10.3.1 Realization of linear voltage processors
10.3.2 Implementation issues
10.4 Alternative switched-circuit techniques
A10.1 Modeling the sampling distortion due to the non-finearity of the switch on-resistance
11 Overview of MOSFET models and parameter extraction for design
11.1 MOSFET models for circuit simulation
11.1.1 Threshold-voltage-based models (BSIM3 and BSIM4)
11.1.2 Surface-potential-based models (HiSIM, MM11, and PSP)
11.1.2.2 The MOS Model 11
11.1.3 Charge-based models (EKV, ACM, and BSIM5)
11.2 Parameter extraction for first-order design
11.2.1 Specific current and threshold voltage
11.3 Comparison between experiment and the ACM model in a 0.35-μm technology
11.4 Comparison between simulation and the ACM model in a 0.13-µm technology
CMOS Analog Design Using All-Region MOSFET Modeling
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