Description
Silicon-On-Insulator (SOI) Technology: Manufacture and Applications covers SOI transistors and circuits, manufacture, and reliability. The book also looks at applications such as memory, power devices, and photonics.
The book is divided into two parts; part one covers SOI materials and manufacture, while part two covers SOI devices and applications. The book begins with chapters that introduce techniques for manufacturing SOI wafer technology, the electrical properties of advanced SOI materials, and modeling short-channel SOI semiconductor transistors. Both partially depleted and fully depleted SOI technologies are considered. Chapters 6 and 7 concern junctionless and fin-on-oxide field effect transistors. The challenges of variability and electrostatic discharge in CMOS devices are also addressed. Part two covers recent and established technologies. These include SOI transistors for radio frequency applications, SOI CMOS circuits for ultralow-power applications, and improving device performance by using 3D integration of SOI integrated circuits. Finally, chapters 13 and 14 consider SOI technology for photonic integrated circuits and for micro-electromechanical systems and nano-electromechanical sensors.
The extensive coverage provided by Silicon-On-Insulator (SOI) Technology makes the book a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics. It is also important for electrical eng
Chapter
1:
Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology
1.2 SOI wafer fabrication technologies: an overview
1.3 SOI volume-fabrication process
1.4 SOI wafer structures and characterization
1.5 Direct wafer bonding: wet surface cleaning techniques
1.6 Characterization of direct bonding mechanisms
1.7 Alternative surface preparation processes for Si and SiO2 direct bonding
1.8 Mass production of SOI substrates by ion implantation, bonding and splitting: Smart Cut ™ technology
1.9 Fabrication of more complex SOI structures
1.10 Fabrication of heterogeneous structures
2:
Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors
2.2 Conventional characterization techniques
2.3 Characterization of SOI wafers using the pseudo-metal oxide semiconductor field effect transister (MOSFET) technique
2.4 Developments in the pseudo-MOSFET technique
2.5 Conventional methods for the characterization of FD MOSFETs
2.6 Advanced methods for the characterization of FD MOSFETs
2.7 Characterization of ultrathin SOI MOSFETs
2.8 Characterization of multiple-gate MOSFETs
2.9 Characterization of nanowire FETs
3: Modeling the performance of short-channel fully depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs)
3.2 The development of SOI MOSFET modeling
3.3 A 1-D compact capacitive model for a SOI MOSFET
3.4 A 2-D analytical model for a SOI MOSFET
3.5 Modeling of dual gate and other types of SOI MOSFET architecture
4:
Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions
4.2 PDSOI technology and devices
4.3 Circuit solutions: digital circuits
4.4 Circuit solutions: static random access memory (SRAM) circuits
4.5 SRAM margining: PDSOI example
5:
Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology
5.2 Planar FDSOI technology
5.3 VT adjustment on FDSOI: channel doping, gate stack engineering and ground planes
5.4 Substrate requirements for FDSOI CMOS devices: BOX and channel thicknesses
5.5 Strain options on FDSOI
5.6 Performance without and with back bias
6:
Silicon-on-insulator (SOI) junctionless transistors
6.3 Models for the junctionless transistor
6.4 Performance comparison with trigate field effect transistors (FETs)
6.5 Beyond the classical SOI nanowire architecture
7:
Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs)
7.2 SOI FinFET device performance
7.3 SOI FinFET substrate optimization
7.4 Process and statistical variability of FinFETs
8: Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology
8.2 Statistical variability in planar fully depleted SOI devices
8.3 Statistical aspects of reliability
8.4 Fin-on-oxide field effect transistors (FinFETs) on SOI
8.5 Summary and future trends
9: Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology
9.2 ESD characterization in SOI devices: SOI transistors
9.3 ESD characterization in SOI devices: SOI diodes
9.4 ESD characterization in SOI devices: fin-on-oxide field effect transistors (FinFETs) and FinDiodes
9.5 ESD characterization in SOI devices: fully depleted SOI (FDSOI) devices
9.6 ESD network optimization in SOI devices
Part II:
Silicon-on-insulator (SOI) devices and applications
10: Silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) for radio frequency (RF) and analogue applications
10.2 Current performance of RF devices
10.3 Limiting factors in MOSFET performance
10.4 Schottky barrier (SB) MOSFETs
10.5 Ultra-thin body ultra-thin BOX (UTBB) MOSFETs
10.6 RF performance of a multi-gate MOSFET: fin-onoxide field effect transistor (FinFET)
10.7 High-resistivity silicon (HR-Si) substrate for SOI technology
11:
Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits for ultralow power (ULP) applications
11.1 Introduction: the importance of ultralow power devices
11.2 Minimizing power consumption of CMOS circuits
11.3 Issues on Vdd scaling to improve the energy efficiency of CMOS circuits
11.4 Developing SOI devices with small variability and adaptive bias control
11.5 Modelling variability
11.6 Device design for ultralow-voltage operation
11.7 Assessing variability in fully depleted silicon-oninsulator (FDSOI) devices
11.8 Assessing the reliability of FDSOI devices
11.9 Circuit design of FDSOI devices
12:
3D integration of silicon-on-insulator (SOI) integrated circuits (ICs) for improved performance
12.2 3D integration using Cu–Cu bonding: generic flow techniques
12.3 3D integration using Cu–Cu bonding: face-to-face silicon layer stacking
12.4 3D integration using Cu–Cu bonding: back-to-face silicon layer stacking
12.5 3D integration using oxide bonding: the MIT Lincoln Laboratory’s ‘face down’ stacking technique
12.6 3D integration using oxide bonding: IBM’s ‘face up’ stacking technique
12.7 3D integration using oxide bonding: the sequential 3D process
12.8 Advanced bonding technology: Cu–Cu bonding
12.9 Advanced bonding technology: dielectric bonding
13:
Silicon-on-insulator (SOI) technology for photonic integrated circuits (PICs)
13.2 Silicon (on insulator) photonics
13.3 Photonic building blocks in SOI
13.4 Device tolerances and compensation techniques
13.5 Advanced stacks for silicon photonics
13.6 Applications of silicon photonics
14: Silicon-on-insulator (SOI) technology for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) sensors
14.2 SOI MEMS/NEMS device structures and principles of operation
14.3 SOI MEMS/NEMS design
14.4 SOI MEMS/NEMS processing technologies
14.5 SOI MEMS/NEMS fabrication
Silicon-On-Insulator (SOI) Technology
：Manufacture and Applications
( Woodhead Publishing Series in Electronic and Optical Materials )
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