Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic*

Author: Yamamoto Shuu’ichirou   Shuto Yusuke   Sugahara Satoshi  

Publisher: Edp Sciences

E-ISSN: 1286-0050|63|1|14403-14403

ISSN: 1286-0042

Source: EPJ Applied Physics (The), Vol.63, Iss.1, 2013-07, pp. : 14403-14403

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Abstract