Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

Publisher: Edp Sciences

E-ISSN: 2100-014x|170|issue|01021-01021

ISSN: 2100-014x

Source: EPJ Web of Conference, Vol.170, Iss.issue, 2018-04, pp. : 01021-01021

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Abstract

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.