An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

ISSN： 0922-5773

Source： Journal of VLSI Signal Processing, Vol.47, Iss.3, 2007-06, pp. : 201-221

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Multiple Templates Access of Trees in Parallel Memory Systems

By Auletta V. de Vivo A. Scarano V.

Journal of Parallel and Distributed Computing, Vol. 49, Iss. 1, 1998-02 ,pp. : 22-39

Academic Press

Access to resources Recommend Favorite

Global Optimization for Mapping Parallel Image Processing Tasks on Distributed Memory Machines

By Lee C. Wang Y.F. Yang T.

Journal of Parallel and Distributed Computing, Vol. 45, Iss. 1, 1997-08 ,pp. : 29-45

Academic Press

Access to resources Recommend Favorite

Towards implementation of a novel scheme for data prefetching on distributed shared memory systems

By Wang Hsiao-Hsi Li Kuan-Ching Lu Ssu-Hsuan Yang Chun-Chieh

The Journal of Supercomputing, Vol. 47, Iss. 2, 2009-02 ,pp. : 111-126

Springer Publishing Company

Access to resources Recommend Favorite

Influence of memory access patterns to small-scale FFT performance

By Lobeiras J.

The Journal of Supercomputing, Vol. 64, Iss. 1, 2013-04 ,pp. : 120-131

Springer Publishing Company

Access to resources Recommend Favorite

An Efficient Architecture for a Lifted 2D Biorthogonal DWT

By Alam Mehboob Badawy Wael Dimitrov Vassil Jullien Graham

Journal of VLSI Signal Processing, Vol. 40, Iss. 3, 2005-07 ,pp. : 335-342

Springer Publishing Company

Access to resources Recommend Favorite