Author: Chung Hsien Tu Che-Min Lwo Ben-Je Lee Chih-Yuan
Publisher: Taylor & Francis Ltd
ISSN: 1362-3060
Source: International Journal of Electronics, Vol.100, Iss.9, 2013-09, pp. : 1256-1269
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
Abstract
Related content
An accurate RLGC circuit model for dual tapered TSV structure
By Zhen Wei Xiaochun Li Junfa Mao
Journal of Semiconductors, Vol. 35, Iss. 9, 2014-09 ,pp. :
An Analog Circuit Fault Characterization Methodology
By Maidon Yvan
Journal of Electronic Testing, Vol. 21, Iss. 2, 2005-04 ,pp. :