Author： Zervas N. D. Masselos K. Karayiannis Y. A. Goutis C. E.
Publisher： Taylor & Francis Ltd
ISSN： 1065-514X
Source： VLSI Design, Vol.14, Iss.3, 2002-01, pp. : 273-286
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Abstract
A systematic methodology for energy dissipation reduction of multimedia applications realized on architectures based on embedded cores and application specific data memory organization is proposed. Performance and area are explicitly taken into account. The proposed methodology includes two major steps: A high-level code transformation step that reorganizes the original description of the target application. The second major step includes the determination of the processor, memory and bus organization of the system and is briefly described. Experimental results from several real-life demonstrators prove the impact of the high level step of the proposed methodology.
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