Design of an Inter-plane Circuit for Clocked PLAs

Author: Wang Chua-Chin   Hsueh Ya-Hsin   Chien Yu-Tsun   Chen Ying-Pei  

Publisher: Taylor & Francis Ltd

ISSN: 1065-514X

Source: VLSI Design, Vol.14, Iss.4, 2002-01, pp. : 373-381

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract