Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Author: Rezaul Hasan S.M.   Wahab Yufridin  

Publisher: Taylor & Francis Ltd

ISSN: 1065-514X

Source: VLSI Design, Vol.15, Iss.2, 2002-01, pp. : 547-553

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Abstract