A vertex cut algorithm for model order reduction of parasitic resistive networks

By Kitanov Petko   Marcotte Odile   Schilders Wil H.A.   Shontz Suzanne M.  

COMPEL: Int J for Computation and Maths. in Electrical and Electronic Eng., Vol. 31, Iss. 6, 2012-11 ,pp. : 1850-1871

Emerald Group Publishing Ltd

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Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

By Robinson William   Wills D.  

Journal of VLSI Signal Processing, Vol. 41, Iss. 1, 2005-08 ,pp. : 65-80

Springer Publishing Company

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On simulation-based probabilistic model checking of mixed-analog circuits

By Clarke Edmund   Donzé Alexandre   Legay Axel  

Formal Methods in System Design, Vol. 36, Iss. 2, 2010-06 ,pp. : 97-113

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DNA and quantum based algorithms for VLSI circuits testing

By Singh Amardeep   Bharadwaj Lalit   Harpreet Singh  

Natural Computing, Vol. 4, Iss. 1, 2005-01 ,pp. : 53-72

Springer Publishing Company

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Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging

By Ishiguro Masami  

Artificial Life and Robotics, Vol. 15, Iss. 3, 2010-09 ,pp. : 325-329

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