A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Author： Zhang Xinwang Chi Baoyong Cao Meng Fu Ling Xia Zhaokang Yin Yun Feng Hongxing Zhang Xing Chiang Patrick Wang Zhihua

Publisher： Springer Publishing Company

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.77, Iss.3, 2013-12, pp. : 567-582

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