Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Author： Martínez Carmen Vallejo Enrique Beivide Ramón Izu Cruz Moretó Miquel

ISSN： 0885-7458

Source： International Journal of Parallel Programming, Vol.34, Iss.3, 2006-06, pp. : 193-211

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Abstract

This paper explores the suitability of dense circulant graphs of degree four for the design of on-chip interconnection networks. Networks based on these graphs reduce the Torus diameter in a factor , which translates into significant performance gains for unicast traffic. In addition, they are clearly superior to Tori when managing collective communications. This paper introduces a new two-dimensional node’s labeling of the networks explored which simplifies their analysis and exploitation. In particular, it provides simple and optimal solutions to two important architectural issues: routing and broadcasting. Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.