Timed verification of the generic architecture of a memory circuit using parametric timed automata

Author: Chevallier Remy   Encrenaz-Tiphene Emmanuelle   Fribourg Laurent   Xu Weiwen  

Publisher: Springer Publishing Company

ISSN: 0925-9856

Source: Formal Methods in System Design, Vol.34, Iss.1, 2009-02, pp. : 59-81

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Abstract