Author: Yu Xining Zhang Yan Patel Ankit Zahrai Allen Weber Mark
Publisher: MDPI
E-ISSN: 2226-4310|3|3|28-28
ISSN: 2226-4310
Source: Aerospace, Vol.3, Iss.3, 2016-09, pp. : 28-28
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Abstract
This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of general purpose digital signal processors. First, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on a Micro Telecom Computing Architecture (MTCA) chassis using the Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebones design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including the Open Computing Language.
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