Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

Author： de Streel Guerric   Bol David  

Publisher： MDPI

E-ISSN： 2079-9268|4|3|168-187

ISSN： 2079-9268

Source： Journal of Low Power Electronics and Applications, Vol.4, Iss.3, 2014-07, pp. : 168-187

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