Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Publisher: John Wiley & Sons Inc

E-ISSN: 1097-007x|43|11|1637-1654

ISSN: 0098-9886

Source: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Vol.43, Iss.11, 2015-11, pp. : 1637-1654

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract