A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 m CMOS

Author： Tang Y. Aktas A. Ismail M. Bibyk S.

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.28, Iss.2, 2001-08, pp. : 195-200

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

A Novel Dual-Modulus 2.8 GHz Divide-by-127/128 Prescaler Using Pull Down Transistor in 0.35  m CMOS Technology

By Rana Ram

Analog Integrated Circuits and Signal Processing, Vol. 42, Iss. 2, 2005-01 ,pp. : 191-195

Springer Publishing Company

Access to resources Recommend Favorite

High-Speed CMOS Track/Hold Circuit Design

By Kobayashi H.

Analog Integrated Circuits and Signal Processing, Vol. 27, Iss. 1-2, 2001-04 ,pp. : 165-176

Springer Publishing Company

Access to resources Recommend Favorite

A 7 GHz 1.5-V Dual-Modulus Prescaler in 0.18 μm Copper-CMOS Technology

By Li S.

Analog Integrated Circuits and Signal Processing, Vol. 32, Iss. 1, 2002-07 ,pp. : 89-95

Springer Publishing Company

Access to resources Recommend Favorite

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

By Flandre D.

Analog Integrated Circuits and Signal Processing, Vol. 21, Iss. 3, 1999-12 ,pp. : 213-228

Springer Publishing Company

Access to resources Recommend Favorite

A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

By Bisdounis L. Gouvetas D. Koufopavlou O.

International Journal of Electronics, Vol. 84, Iss. 6, 1998-06 ,pp. : 599-613

Taylor & Francis Ltd

Access to resources Recommend Favorite