Author： Strak Adam
Publisher： Springer Publishing Company
ISSN： 0925-1030
Source： Analog Integrated Circuits and Signal Processing, Vol.41, Iss.2-3, 2004-12, pp. : 223-236
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Abstract
This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital Converter (ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that it is stochastic white Gaussian noise. Using this assumption, the ΣΔ performance is characterized in terms of Signal-to-Jitter-Noise-Ratio (SJNR) for each jitter effect. Non-uniform sampling effects have, to some extent, been characterized in litterature (S.R. Norsworthy, R. Schreier and G.C. Temes, Delta-Sigma Data Converters</i>—Theory, Design and Simulation</i>, IEEE Press, New Jersey, 1997). However, varying phase-length effects are also a main focus in this work since they can have a significant impact on the total ADC performance depending on settling accuracy and characteristic. Furthermore, because SC circuits usually operate on a two-phase clock, jitter may give rise to a secondary effect, phase overlap, which does not appear when dealing with a single-phase clock. This effect severely degrades the resolution of a ΣΔ and therefore a thorough understanding of the interaction of jitter on the two phases is necessary.
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