Author： Liu F. Lau K. T. Siek L. Chan P. K.
Publisher： Taylor & Francis Ltd
ISSN： 1362-3060
Source： International Journal of Electronics, Vol.86, Iss.3, 1999-03, pp. : 323-328
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Abstract
An improved low-power compact logic structure with a simple clock supply is presented. It is based on adiabatic switching principles. A comparison, made between the proposed structure and the previous structure, shows about 37% transistor count saving for the 1-bit full adder and 43% area saving for the 2-NAND/AND gate. HSPICE simulations validate that the power dissipations are at a comparable level with those of the previous adiabatic structure and are much lower than those of conventional static CMOS.
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