Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

Author: Kim J. B.  

Publisher: Taylor & Francis Ltd

ISSN: 1362-3060

Source: International Journal of Electronics, Vol.94, Iss.10, 2007-10, pp. : 905-913

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract