Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

Author: Sugimoto Y.   Sekiya M.  

Publisher: Springer Publishing Company

ISSN: 0925-1030

Source: Analog Integrated Circuits and Signal Processing, Vol.20, Iss.2, 1999-08, pp. : 149-153

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract