Novel layout technique for on-chip inductance minimization

Author: Dao V.T.S.   Etoh T.G.   Tanaka M.   Akino T.  

Publisher: Emerald Group Publishing Ltd

ISSN: 1356-5362

Source: Microelectronics International, Vol.26, Iss.3, 2009-07, pp. : 3-8

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Abstract