A new pipelined analog-to-digital converter using current conveyors

Author： Hwang Yuh-Shyan   Chen Jiann-Jong   Wu Sing-Yen   Liao Lu-Po   Tsai Chia-Chun  

Publisher： Springer Publishing Company

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.50, Iss.3, 2007-03, pp. : 213-220

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

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Abstract

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm2.

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