Area efficient digital logic NOT gate using single electron box (SEB)

Author: Bahrepour Davoud  

Publisher: Edp Sciences

E-ISSN: 1779-6288|8|issue|A6-A6

ISSN: 1779-627x

Source: International Journal for Simulation and Multidisciplinary Design Optimization, Vol.8, Iss.issue, 2017-01, pp. : A6-A6

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Abstract