A low-power DCO using inverter interlaced cascaded delay cell

ISSN： 1674-4926

Source： Journal of Semiconductors, Vol.35, Iss.11, 2014-11, pp. : 115004-115009

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme

By Lim Jinup Choi Joongho

Analog Integrated Circuits and Signal Processing, Vol. 49, Iss. 3, 2006-12 ,pp. : 359-365

Springer Publishing Company

Access to resources Recommend Favorite

Power Loss Investigation for 13-level Cascaded H-Bridge Multilevel Inverter

Journal of Energy and Power Sources, Vol. 2, Iss. 6, 2015-06 ,pp. : 230-238

Ethan Publishing Company

Access to resources Recommend Favorite

A Low-Power Block-Matching Cell for Video Compression

By Tartagni M.

Analog Integrated Circuits and Signal Processing, Vol. 27, Iss. 3, 2001-05 ,pp. : 259-271

Springer Publishing Company

Access to resources Recommend Favorite

Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

By Adler V. Friedman E.G.

Analog Integrated Circuits and Signal Processing, Vol. 14, Iss. 1-2, 1997-09 ,pp. : 29-39

Springer Publishing Company

Access to resources Recommend Favorite

Low-Power CMOS Analog Signal Processing Using Spatial Mapping

By Nsgmaeligss S.

Analog Integrated Circuits and Signal Processing, Vol. 18, Iss. 1, 1999-01 ,pp. : 79-88

Springer Publishing Company

Access to resources Recommend Favorite