Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

Publisher： Trans Tech Publications

E-ISSN： 1662-9752|2016|858|1112-1116

ISSN： 0255-5476

Source： Materials Science Forum, Vol.2016, Iss.858, 2016-06, pp. : 1112-1116

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

By  

Materials Science Forum, Vol. 2016, Iss. 858, 2016-06 ,pp. : 908-912

Trans Tech Publications

Access to resources Recommend Favorite

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

By  

Materials Science Forum, Vol. 2016, Iss. 858, 2016-06 ,pp. : 663-666

Trans Tech Publications

Access to resources Recommend Favorite

Alkali Metal Re-Distribution after Oxidation of 4H-SiC

By  

Materials Science Forum, Vol. 2016, Iss. 858, 2016-06 ,pp. : 677-680

Trans Tech Publications

Access to resources Recommend Favorite

Dielectric films fabricated in plasma as passivation of 4H-SiC Schottky diodes

By Sochacki M.   Szmidt J.  

Thin Solid Films, Vol. 446, Iss. 1, 2004-01 ,pp. : 106-110

Elsevier

Access to resources Recommend Favorite

Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11-20) and (1-100) Faces

By  

Materials Science Forum, Vol. 2015, Iss. 821, 2015-07 ,pp. : 721-724

Trans Tech Publications

Access to resources Recommend Favorite