Design optimization of ESD protection and latchup prevention for a serial I/O IC

Author： Huang C.-Y. Chen W.-F. Chuan S.-Y. Chiu F.-C. Tseng J.-C. Lin I.-C. Chao C.-J. Leu L.-Y. Ker M.-D.

Publisher： Elsevier

ISSN： 0026-2714

Source： Microelectronics Reliability, Vol.44, Iss.2, 2004-02, pp. : 213-221

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