Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

By Deshmukh Jyoti   Khare Kavita  

International Journal of Electronics, Vol. 99, Iss. 12, 2012-12 ,pp. : 1717-1728

Taylor & Francis Ltd

Access to resources Recommend Favorite

Dynamic current testing for CMOS domino circuits

By Nazer Anis   Chehab Ali   Kayssi Ayman  

International Journal of Electronics, Vol. 95, Iss. 6, 2008-01 ,pp. : 577-592

Taylor & Francis Ltd

Access to resources Recommend Favorite

Robust Low Power CMOS Single-Ended to Fully-Balanced Converter Circuits

By Elwan H.  

Analog Integrated Circuits and Signal Processing, Vol. 19, Iss. 2, 1999-05 ,pp. : 169-179

Springer Publishing Company

Access to resources Recommend Favorite

Dynamic Power Supply Current Testing of CMOS SRAMs

By Liu J.  

Journal of Electronic Testing, Vol. 16, Iss. 5, 2000-10 ,pp. : 499-511

Springer Publishing Company

Access to resources Recommend Favorite

A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

By Bisdounis L.   Gouvetas D.   Koufopavlou O.  

International Journal of Electronics, Vol. 84, Iss. 6, 1998-06 ,pp. : 599-613

Taylor & Francis Ltd

Access to resources Recommend Favorite