An accurate transient model for BiCMOS gate optimization

By Jimenez Vicente   Alcubilla Ramon  

International Journal of Electronics, Vol. 82, Iss. 5, 1997-05 ,pp. : 503-514

Taylor & Francis Ltd

Access to resources Recommend Favorite

Modelling and testing for bridging faults in CMOS and BiCMOS combinational circuits

By Ismaeel Asad A.   Bhatnagar Rakesh  

International Journal of Electronics, Vol. 83, Iss. 4, 1997-10 ,pp. : 529-540

Taylor & Francis Ltd

Access to resources Recommend Favorite

BiCMOS domino: a novel high-speed dynamic BiCMOS logic

By Menon Sankaran M.   Jayasumana Anura P.   Malaiya Yashwant K.  

International Journal of Electronics, Vol. 83, Iss. 2, 1997-08 ,pp. : 177-190

Taylor & Francis Ltd

Access to resources Recommend Favorite

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

By Gan Kwang-Jow  

Analog Integrated Circuits and Signal Processing, Vol. 59, Iss. 2, 2009-05 ,pp. : 161-167

Springer Publishing Company

Access to resources Recommend Favorite

Analysis of the metastable behaviour of a BiCMOS SR latch

By Bahbouh Hussein T.   Khalil Ahmed H.   Salama Aly E.  

International Journal of Electronics, Vol. 87, Iss. 4, 2000-04 ,pp. : 425-435

Taylor & Francis Ltd

Access to resources Recommend Favorite