Design procedure for two-stage CMOS opamp with optimum balancing of speed, power and noise

Author: Chandrawat Uday Bhanu Singh   Mishra D. K.  

Publisher: Taylor & Francis Ltd

ISSN: 1362-3060

Source: International Journal of Electronics, Vol.96, Iss.11, 2009-11, pp. : 1145-1159

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Abstract