Delay analysis of a single voltage-scaled-repeater driven long interconnect

Author： Chandel Rajeevan Sarkar S Agarwal R.P.

ISSN： 1356-5362

Source： Microelectronics International, Vol.22, Iss.3, 2005-03, pp. : 28-33

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Abstract

Purpose - To study the effect of voltage-scaling on output voltage waveform, delay and power dissipation in a single inverter/repeater driven interconnect load, in different technology nodes. Design/methodology/approach - An analytical expression for the output voltage of a single CMOS-inverter/repeater driven long interconnects is developed. Delay analysis by the use of this expression, for long interconnects, modeled as RLC load, is compared with SPICE simulations. Good agreement between analytical and SPICE derived results is obtained. Findings - The model works well for both sub-micron and nanometer CMOS technologies. The maximum error in 90 percent fall time of output voltage is 7.5, 2.6 and 0.28 percent in 0.8 m, 0.18 m and 70 nm technologies, respectively. The maximum inaccuracy in case of high to low 50 percent propagation delay is about 5 percent for 0.8 m, 3.1 percent for 0.18 m and 2.3 percent in case of 70 nm technologies. The model shows a very good accuracy for nanometer technologies. The analysis shows that the use of scaled technologies along with voltage-scaling leads to significant saving in power as well as delay improvement of a repeater driven long interconnect. Originality/value - A new compact analytical expression for the output voltage of a single CMOS-inverter driven long RLC interconnects is developed. The analysis carried out in the paper is of value to low-power VLSI interconnect design.