Author： Trinitis Carsten Küstner Tilman Weidendorfer Josef Smajic Jasmin
Publisher： Springer Publishing Company
ISSN： 0920-8542
Source： The Journal of Supercomputing, Vol.57, Iss.2, 2011-08, pp. : 132-140
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Abstract
This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products.Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.
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