Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Publisher： IGI Global_journal

E-ISSN： 1947-3184|1|1|86-101

ISSN： 1947-3176

Source： International Journal of Embedded and Real-Time Communication Systems (IJERTCS), Vol.1, Iss.1, 2010-01, pp. : 86-101

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Reliable network-on-chip design for multi-core system-on-chip

By Chang Kuei-Chung  

The Journal of Supercomputing, Vol. 55, Iss. 1, 2011-01 ,pp. : 86-102

Springer Publishing Company

Access to resources Recommend Favorite

Integrated modelling and generation of a reconfigurable network-on-chip

By Ching Doris   Schaumont Patrick   Verbauwhede Ingrid  

International Journal of Embedded Systems, Vol. 1, Iss. 3-4, 2006-06 ,pp. : 218-227

Inderscience Publishers

Access to resources Recommend Favorite

High-throughput differentiated service provision router architecture for wireless network-on-chip

By Wang Chifeng  

International Journal of High Performance Systems Architecture, Vol. 4, Iss. 1, 2012-06 ,pp. : 38-56

Inderscience Publishers

Access to resources Recommend Favorite

A highly efficient behavioural model of router for network-on-chip with link aggregation

By Korotkyi Ievgen   Lysenko Oleksandr  

International Journal of Embedded Systems, Vol. 5, Iss. 1-2, 2013-02 ,pp. : 3-12

Inderscience Publishers

Access to resources Recommend Favorite

Generating Process Network Communication Infrastructure for Custom Multi-Core Platforms

By  

International Journal of Embedded and Real-Time Communication Systems (IJERTCS), Vol. 1, Iss. 1, 2010-01 ,pp. : 37-63

IGI Global_journal

Access to resources Recommend Favorite