MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-CIRCUITS DUE TO ELECTROSTATIC DISCHARGE

Publisher： Edp Sciences

E-ISSN： 0449-1947|49|C4|C4-303-C4-306

ISSN： 0449-1947

Source： Le Journal de Physique Colloques, Vol.49, Iss.C4, 1988-09, pp. : C4-303-C4-306

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Related content

LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDERING POWER-ON TRANSIENTS

By  

Le Journal de Physique Colloques, Vol. 49, Iss. C4, 1988-09 ,pp. : C4-49-C4-52

Edp Sciences

Access to resources Recommend Favorite

MAXIMUM OPERATING VOLTAGE LIMITATIONS DUE TO PARASITIC BIPOLAR ACTION IN VLSI CMOS

By  

Le Journal de Physique Colloques, Vol. 49, Iss. C4, 1988-09 ,pp. : C4-387-C4-390

Edp Sciences

Access to resources Recommend Favorite

A novel diode string triggered gated-PiN junction device for electrostatic discharge protection in 65-nm CMOS technology

By Li-Zhong Zhang   Yuan Wang   Guang-Yi Lu   Jian Cao   Xing Zhang  

Chinese Physics B, Vol. 24, Iss. 10, 2015-10 ,pp. : 108503-108507

IOP Publishing

Access to resources Recommend Favorite

POWER MOS FET MODELS FOR "SWITCHING" CIRCUITS

By  

Le Journal de Physique Colloques, Vol. 49, Iss. C4, 1988-09 ,pp. : C4-621-C4-624

Edp Sciences

Access to resources Recommend Favorite

MOS Current Mode Logic Near Threshold Circuits †

By Shapiro Alexander   Friedman Eby G.  

Journal of Low Power Electronics and Applications, Vol. 4, Iss. 2, 2014-06 ,pp. : 138-152

MDPI

Access to resources Recommend Favorite