CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

By Shauly Eitan N.  

Journal of Low Power Electronics and Applications, Vol. 2, Iss. 1, 2012-01 ,pp. : 1-29

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A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

By Beshay Peter   Ryan Joseph F.   Calhoun Benton H.  

Journal of Low Power Electronics and Applications, Vol. 3, Iss. 2, 2013-05 ,pp. : 159-173

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Path Specific Register Design to Reduce Standby Power Consumption

By Salman Emre   Qi Qi  

Journal of Low Power Electronics and Applications, Vol. 1, Iss. 1, 2011-04 ,pp. : 131-149

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Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

By Liu Yifei   Furth Paul M.   Tang Wei  

Journal of Low Power Electronics and Applications, Vol. 5, Iss. 4, 2015-11 ,pp. : 234-256

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Untrimmed Low-Power Thermal Sensor for SoC in 22 nm Digital Fabrication Technology

By Eitan Ro’ee   Cohen Ariel  

Journal of Low Power Electronics and Applications, Vol. 4, Iss. 4, 2014-12 ,pp. : 304-316

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