Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

Publisher： John Wiley & Sons Inc

E-ISSN： 1097-007x|43|7|854-865

ISSN： 0098-9886

Source： INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Vol.43, Iss.7, 2015-07, pp. : 854-865

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