Logic Design Validation via Simulation and Automatic Test Pattern Generation

By Al-asaad H.  

Journal of Electronic Testing, Vol. 16, Iss. 6, 2000-12 ,pp. : 575-589

Springer Publishing Company

Access to resources Recommend Favorite

Hierarchical robust test generation for CMOS circuit stuck-open faults

By Tsiatouhas Y.   Haniotakis Th.   Nikolos D.   Paschalis A.   Halatsis C.  

International Journal of Electronics, Vol. 82, Iss. 1, 1997-01 ,pp. : 45-60

Taylor & Francis Ltd

Access to resources Recommend Favorite

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

By Chen W-Y.  

Journal of Electronic Testing, Vol. 18, Iss. 1, 2002-02 ,pp. : 17-28

Springer Publishing Company

Access to resources Recommend Favorite

Bridging Faults in Pipelined Circuits

By Favalli M.  

Journal of Electronic Testing, Vol. 16, Iss. 6, 2000-12 ,pp. : 617-629

Springer Publishing Company

Access to resources Recommend Favorite

A Ring Architecture Strategy for BIST Test Pattern Generation

By Fagot C.  

Journal of Electronic Testing, Vol. 19, Iss. 3, 2003-06 ,pp. : 223-231

Springer Publishing Company

Access to resources Recommend Favorite