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Period of time: 2007年3期
Publisher: Springer Publishing Company
Founded in: 1989
Total resources: 30
ISSN: 0922-5773
Subject: TP Automation Technology , Computer Technology
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
The Journal of VLSI Signal Processing,volume 39,issue 3
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IEEE-Compliant IDCT on FPGA-Augmented TriMedia
By Sima Mihai,Cotţofaná Sorin,Eijndhoven Jos,Vassiliadis Stamatis,Vissers Kees in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
By Shoa Alireza,Shirani Shahram in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Adaptive-Hierarchical-Filtering Technique for High-Quality Magazine Image Reproduction
By Lin Tsung,Shu Joseph in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture
By Meribout Mahmound,Nakanishi Mamoru in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Digital Signal Processing with Interleaved ADC Systems
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation
By O’Neil Timothy,Sha Edwin in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
By Leeser Miriam,Coric Srdjan,Miller Eric,Yu Haiqian,Trepanier Marc in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
A New Low Latency Parallel FIR Filter Scheme
By Kalivas Paraskevas,Vassilakis Vassilis,Meletis Chris,Pekmestzi Kiamal in (2005)
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.![](/images/ico/ico5.png)
Pipelined IIR Filter Architecture Using Pole-Radius Minimization
The Journal of VLSI Signal Processing,volume 39,issue 3 , Vol. 39, Iss. 3, 2005-03 , pp.