Author： Mannino C. Rabah H. Weber S. Tanougast C. Berviller Y. Janiaut M.
Publisher： Taylor & Francis Ltd
ISSN： 1362-3060
Source： International Journal of Electronics, Vol.93, Iss.6, 2006-06, pp. : 373-383
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
Abstract
Measurement of quality of service in digital video broadcasting requires particularly the real-time monitoring of program clock reference (PCR) parameters for all the programs contained within the MPEG-2 transport stream. To achieve this, an all digital solution based on a novel all-digital phase locked loop (ADPLL) was proposed, allowing one to cast off the analog components and then a full FPGA implementation. The complexity of the system increases with the number of programs to be processed and an architectural optimization is then necessary. In this paper, several architectures are explored, considering area and objectives throughout. This exploration is based on hard-ware synthesis and code compilation results of system tasks. Three main cases are studied: hardware parallel implementation; hardware blocs reuse and hardware/software implementation. Experimental results are presented and discussed.
Related content
Access to resources
Recommend
