Low Energy, Low Latency and High Speed Array Divider Circuit Using a Shannon Theorem Based Adder Cell

Publisher： Bentham Science Publishers

E-ISSN： 2212-4020|3|1|61-72

ISSN： 1872-2105

Source： Recent Patents on Nanotechnology, Vol.3, Iss.1, 2009-01, pp. : 61-72

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

By  

Recent Patents on Computer Science, Vol. 9, Iss. 3, 2017-01 ,pp. : 216-221

Bentham Science Publishers

Access to resources Recommend Favorite

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

By  

Recent Patents on Engineering, Vol. 1, Iss. 2, 2007-06 ,pp. : 131-145

Bentham Science Publishers

Access to resources Recommend Favorite

Nanotechnology Based Green Energy Conversion Devices with Multifunctional Materials at Low Temperatures

By  

Recent Patents on Nanotechnology, Vol. 11, Iss. 2, 2017-07 ,pp. : 85-92

Bentham Science Publishers

Access to resources Recommend Favorite

Signal recording system based on a LabVIEWTM virtual instrument using a multichannel high speed ADC

By Popov A.   Labutin T.  

Measurement Techniques, Vol. 54, Iss. 2, 2011-05 ,pp. : 213-218

Springer Publishing Company

Access to resources Recommend Favorite

Advanced Electrical Power Generation Technology Using Renewable & Clean Low-Enthalpy Geothermal Energy Sources

By  

Recent Patents on Mechanical Engineering, Vol. 4, Iss. 2, 2011-05 ,pp. : 168-179

Bentham Science Publishers

Access to resources Recommend Favorite