VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Publisher: Bentham Science Publishers

ISSN: 2213-2759

Source: Recent Patents on Computer Science, Vol.9, Iss.3, 2017-01, pp. : 216-221

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract