Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology †

Author： Batra Pooja   Skordas Spyridon   LaTulipe Douglas   Winstel Kevin   Kothandaraman Chandrasekharan   Himmel Ben   Maier Gary   He Bishan   Wehella Gamage Deepal   Golz John   Lin Wei   Vo Tuan   Priyadarshini Deepika   Hubbard Alex   Cauffman Kristian   Peethala Brown   Barth John   Kirihata Toshiaki   Graves-Abe Troy   Robson Norman   Iyer Subramanian  

Publisher： MDPI

E-ISSN： 2079-9268|4|2|77-89

ISSN： 2079-9268

Source： Journal of Low Power Electronics and Applications, Vol.4, Iss.2, 2014-05, pp. : 77-89

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