Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

Publisher： IOP Publishing

E-ISSN： 1361-6528|25|50|505604-505614

ISSN： 0957-4484

Source： Nanotechnology, Vol.25, Iss.50, 2014-12, pp. : 505604-505614

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Nanographene charge trapping memory with a large memory window

By  

Nanotechnology, Vol. 26, Iss. 45, 2015-11 ,pp. : 455704-455708

IOP Publishing

Access to resources Recommend Favorite

Effect of Charge Trapping on the Asymmetrical Shift of Memory Window in MFIS Devices

By Lee Y. W.   Kang D.   Roh Y.   Lee S. K.   Kim Y.  

Integrated Ferroelectrics, Vol. 49, Iss. 1, 2002-01 ,pp. : 31-40

Taylor & Francis Ltd

Access to resources Recommend Favorite

Comparison of MFMOS and MFOS One Transistor Memory Devices

By Li Tingkai   Hsu Sheng Teng   Ulrich Bruce   Evans Dave  

Integrated Ferroelectrics, Vol. 48, Iss. 1, 2002-01 ,pp. : 91-99

Taylor & Francis Ltd

Access to resources Recommend Favorite

Effect of Pre-annealing to Blocking Oxide on the Performance of Dual Trapping-layer Engineered Charge Trapping Memory

By Chen Guoxing   Huo Zongliang   Han Yulong   Li Xinkai   Zhang Dong   Liu Su   Liu Ming  

Integrated Ferroelectrics, Vol. 151, Iss. 1, 2014-02 ,pp. : 56-60

Taylor & Francis Ltd

Access to resources Recommend Favorite

MULTI-BIT STORAGE BASED ON CHALCOGENIDE THIN FILM TRANSISTOR FOR HIGH DENSITY NONVOLATILE MEMORY APPLICATION

By CAI YANFEI   ZHOU PENG   TANG TINGAO   GAO CHARLES   LIN YINYIN  

Integrated Ferroelectrics, Vol. 110, Iss. 1, 2009-01 ,pp. : 34-42

Taylor & Francis Ltd

Access to resources Recommend Favorite